By Muhammad S. Elrabaa
Advanced Low-Power electronic Circuit Techniques provides a number of novel excessive functionality electronic circuit designs that emphasize low-power and low-voltage operation. those circuits symbolize a variety of circuits which are utilized in cutting-edge VLSI structures and for this reason function stable examples for low-power layout. every one bankruptcy features a short creation that serves as a brief heritage and provides the incentive at the back of the layout. every one bankruptcy additionally ends with a precis that in brief explains the contributions contained therein. This makes the publication very readable. The reader can skim throughout the chapters in a short time to get a think for the layout difficulties offered within the booklet and the options proposed by way of the authors. Examples of circuits utilized in platforms the place low-power is necessary from reliability and portability issues of view (such as general-purpose and DSP processors) are offered in Chapters 2, three and four. Chapters five and seven supply examples of circuits utilized in structures the place reliability and extra method integration are the most riding forces in the back of decreasing the facility intake. bankruptcy 6 offers an instance of a normal function high-performance low-power circuit layout.
Advanced Low-Power electronic Circuit Techniques is a true designer's publication. It investigates substitute circuit kinds, in addition to architectural possible choices, and provides quantitative effects for comparability in life like applied sciences. a number of of the circuits offered were fabricated in order that simulations will be checked. The circuits lined are crucial development blocks for plenty of designs, so the textual content may be of direct use to designers. MOS designs are coated, in addition to BiCMOS, and there are numerous novel circuits.
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Additional info for Advanced Low-Power Digital Circuit Techniques
2 Low-Po wer High-Performan ce A dders 21 60 CPL-CLA ~ DPL-CLA ~ TG -CLA IlJl TG-MAN m TG-CS ~ Cony . CSA-CPL LJ CSA-TG 0 50 40 - 30 • (/) c:: >. 8 Effect of V D D scaling o n the adders ' d elay. LO ...... -CLA CSA-CPL 0 CSA-TG 0 1500 -.. 9 MHz. 7 LAYOUT STRATEGY The CSA-CPL circuit was laid out for fabrication in order to perform an experimental evaluation of the circuit. 8Jlm CMOS (in BiCMOS) process . In constructing the circuit layout, consideration was given to minimizing the critical path routing capacitance.
To further enhance the Wallace tree multiplier, the modified Booth algorithm can be used to reduce the number of partial products by half in a carry-save adder array. 8. It consists of four functions: the Booth encoder, the partial product's generator, the compressor blocks, and the final 64-bit adderi . The Wallace tree is constructed with 3 stages (levels). The first stage has 4 blocks (A to D), with each block summing up 4 partial 41 Low-P ower High-Performance Multipli ers ? o 7 :Zero x :Bit j umping level ••• • :Partiel product _ Bit generated by compressor 1st stage g 0 00 0 00 - - - - - - - x- - - - - -- - - - xx - - - x - - - -- - - - - X X -- -X !
Complementary signals are available which is compatible with the proposed adder architecture and eliminate the use of inverters in th e conditional circuit. ~ Multiplexers "V , Double Ended Restoration ;,.. 3 out Co ut CSA-CPL-like schematic of the output stage. e. 3. The output stage is shown because it contains all elem ents of the design. The conditional cell and the MUXs are designed using CPL logic. The conditional Low-Power High-Performance Adders 13 circuit generates the double sum and carry and their complement with a reduced swing , and then the generated signals drive the MUXs without the need for signal restoration.
Advanced Low-Power Digital Circuit Techniques by Muhammad S. Elrabaa